Butterfly Fat Tree Network on FPGA

From June to August 2017, I was a student researcher as part of the University of Pennsylvania SUNFEST Research Experience for Undergraduate Program.

I worked with Professor Andre DeHon to develop a relatively new Network-on-Chip topology called a Deflection-routed Butterfly Fat Tree (BFT).

The network is constructed using verilog and python, and is simulated and tested using both python and the iverilog simulator.