# Circuit Series III: Voltage Bias Circuit

### Introduction

Often in analog circuit design, it is desirable to have good control over current sources. An ideal current source has infinite output resistance. A single transistor current source has the same output resistance as the transistor, namely $r_o$ which is approximately 400k$\Omega$ in the 180nm process used in this project description.

Cascoding a current source, however, boosts output resistance by an open loop gain factor, to $g_m r_{o1} r_{o2} + r_{o1} + r_{02} \approx g_m r_o ^2$. Using the table in Circuit Series Introduction and Characterization, an nmos cascode current source output resistance can be approximated as 27.2 M$\Omega$! This approximation of course assumes that both transistors in the cascode structure are in saturation, and that $V_{GS} = 0.5V$. The latter requirement means that gate voltages must not only accurate, but precise as well. Variation in $V_{GS}$ on a current source means variation in output current, and leads to noise in whatever topology that includes that current source.

How can a good bias voltage on the gates of cascode current sources be implemented? A resistive divider could be hypothetically used, except it would be subject to mismatch effects, power supply variation, ground noise, and temperature variations.

### Description

#### Beta Multiplier Reference (BMR)

Reliable supply independent biasing is needed. One notable topology is the beta multiplier reference. The beta multiplifer reference allows the current source to be tuned through a resistor (which can include fuses that allow adjustment post fabrication). The beta multiplifer reference can notably source a relatively constant current independent of variations in $V_{DD}$, and allows the designer to consider more so the current that they would like to source/sink, rather than the bias voltage that leads to that current. The schematic for the short channel beta multiplier reference circuit is shown below:

In this topology, M3 and M4 both have the same gate voltage, and thus are able to exert a large amount of control over the reference currents $I_{ref1}$ and $I_{ref2}$ and ensure that they are close to identical. The drain currents of M3 and M4 is determined by the diff-amp, surrounded by the dashed box. Note that if $V_{reg}$ increases by a small amount above $V_{biasn}$, the change is amplified by the diff-amp, leading to an increase in M4's gate voltage and a decrease in $I_{ref2}$. This decreases $V_{reg}$ -- negative feedback! Simulatenously, M3's gate voltage also increases and $V_{biasn}$ is decreased, but only to the point where it matches $V_{reg}$.

$V_{biasn}$ does not go further down, because the topology enforces that negative feedback is greater than positive feedback around the loops of the diff-amp and M3 and M4, which act like common-source amplifiers. The net effect is that $V_{reg}$ enforces stable currents through both sides of the BMR, and the resistor determines what $V_{reg}$ will be, independent of any other individual voltage present in the circuit.

The output of the BMR is two voltages: $V_{biasp}$ and $V_{biasn}$. To stabilize the circuit, we will add a large capacitance at $V_{biasp}$. Recall that the bias voltages do not drive any load, they simply must serve as a constant voltage. Therefore, the greater the capacitance present at $V_{biasp}$, the more stable it will be.

Also note that we must include a start-up circuit, added below, to ensure that the other stable operating point of the circuit, where $V_{biasn}=0$ and $V_{biasp}=V_{DD}$, cannot occur. The transistor MSU3 should draw only enough current to ensure that the BMR works. It is turned off once BMR stabilizes at its functional operating point.

...to be continued!