Circuit Series II: Current-Steering Digital-to-Analog Converter


The current-steering digital-to-analog converter (DAC) topology is a common and effective method to convert digital voltage signals to analog currents. The topology allows the engineer to design a 1-bit cell, which can be used to build an array of cells with N-bit precision. Metrics such as DNL, INL, offset, and gain are determined to characterize the effectiveness of the design. Simulations utlize a TSMC 0.18um model library, however any MOSFET model library can be substituted with the expectation that the metrics will differ.

Current project repository: Git


Current-Steering Cell

Fundamentally, the current-steering DAC can be considered an array of 1-bit cells.


1-bit current-steering cell

Each cell accepts a single digital input to a gate of a transistor. When input is LOW, the PMOS transistor M1 is ON and permits current to flow from the current source to the output. When input is HIGH, the PMOS transistor M1 is OFF and prevents current from flowing to the output.

If differential signals are desired, the topology can include an additional transistor that accepts the complement of the digital input. In the topology shown above, the complementary output is steered by M2. In this manner, current is steered from the current-source to one of two outputs: the plus output, Iop, which is an analog current that is proportional to the digital input signal, and the minus output, Iom, which is an analog current that is proportional to the one's complement of the digital input signal. The amount of current-steered depends on the bias set on the current source, Vbp, and differs depending on application.

We can isolate the gate of the transistor from the input of the cell by making use of inverters to buffer the digital input. Buffering can decrease capacitive loading at the input of the cell and guarantees relatively constant capacitances at the input compared to driving the switch transistors directly.

N-bit Resolution

How can a DAC with greater than 1-bit resolution be implemented? It can be noted that, for a 2-bit DAC, the most significant bit should produce twice as much current as the least significant bit, at either the plus or minus output, depending on the parity of the bit. For a 3-bit DAC, the MSB should produce 4 times the current as the LSB. For an N-bit DAC, the MSB must produce 2^(N-1) as much current as the LSB. Therefore the MSB must drive 2^(N-1) current cells, the next MSB must drive 2^(N-2) current cells, and so-on. For an N-bit DAC, there will be (2^N)-1 current cells. The respective positive or negative outputs of all the current cells are all connected as a single node (positive-to-positive, negative-to-negative).

The final topology can be shown as below, for a 4-bit DAC.


4-bit current-steering DAC schematic

Note that the significance of the bit determines the scale factor of the corresponding one-bit cell i.e. D3 is an input to a cell scaled by a factor of 8.



The 4-bit DAC is simulated using transient analysis with a 4-bit counter as input. The LSB has a period of 100ns, thus each analog output signal has 49ns to settle to a value before the digital input signal increments. Ideally, a 49ns latency (corresponding to 1/100ns = 10 MHz input frequency) is sufficient to acheive 4-bit resolution.


4-bit DAC Transient Analysis with Counter Input

The waveform generates a typical 'staircase'-like pattern. Typical output glitches on the scale of 129uA = 57 LSB! It is important to ensure that the load of the topology can handle these spikes.

There is a strange change in the positive output signal with a digital input of 0001. The signal initially settles at one analog value and gradually increases to settle at another value. At no other point does the output behave in this manner.


Numpy and Matplotlib are used to analyze the transient analysis for INL, DNL, and offset.

Output from command:

One LSB Current is: 2.2331021235545216e-06
Max DNL: 0.02865813997913158
Offsets (percent of LSB): [2.36547154e-03 1.46182464e+03]
Max INL: 0.3817549337872954

Sample points are 1ns before the digital input signal changed, corresponding to a latency <= 49ns, as described above.

the LSB current is defined as the sum of both plus and minus output signals (corresponding to 15 ON current cell output), at each sample point, divided by 15 * total number of samples. In the analysis, 1 LSB corresponds to 2.23 uA.


INL, or integral non-linearity, is defined as the difference between the analog output versus expected analog output, in units of LSB.


INL error

The worst case INL is 0.382 LSB. INL must be less than 0.5 LSB to be considered N-bit resolution. If the worst case INL straddles or exceeds 0.5 LSB, it can be reduced by either increasing the 1 LSB current, which effectively minimizes the effects of subthreshhold conduction from the OFF transistors, or by increasing the current source's output resistance i.e. cascoding.


DNL, or differential non-linearity, is defined as the difference between the 'step height' and one LSB. The step height is the difference between the analog output for a particular digital input signal and the analog output for the previous digital input.


DNL error

The absolute value of DNL is well below 0.5 LSB, thus does not impact the resolution of the DAC.


Offset for both positive and negative rails is on the scale of 10^-5 LSB and is thus insignificant. The result of offset is the the sum of the subthreshhold current of the current cells, which is very small.


A 4-bit current-steering DAC with a 0.18um transistor feature size is simulated at 100 MHz. INL, DNL, and offset all meet specifications to ensure the DAC is effective in integrated circuit applications.