# Circuit Series: Introduction and Characterization

### Justification

As part of my coursework, I have had some growing experience designing circuits. I plan on documenting these different topologies as distinct projects. I will describe how the circuits work and describe the various metrics that quanitfy their efficacy.

### Software

SPICE simulator: ngspice

Circuit drawing: Xcircuit

Layout: Electric

Analysis & graphing: Python3 with numpy, matplitlib packages

Repository: https://gitlab.com/nmg

## Characterization

In CMOS: Design, Layout, and Simulation text, Baker characterizes both a $\lambda=25nm$ and a $\lambda=250nm$ CMOS process. While hundreds of examples, including the files for simulations and model decks, are included, the models do not represent real devices. Below I will characterize a 180nm ($\lambda=100nm$) process.

### Determining Tuning Parameters

#### Gate Length

There is a trade-off between power and speed in any CMOS design. Baker's CMOS text has excellent analysis of various important MOSFET parameters (tables 9.1 and 9.2).

Transition frequency $f_T$ (frequency in which the transistor transitions from an amplifier to attenuator) for short channel devices can be shown to be:

Thus:

I will follow the text's recommendations for a gate length of 2-5 times minimum for general analog design.

Why not minimum length? While minimum length devices are often used in digital circuits (where precision matters less), they suffer from mismatch effects. Furthermore, channel length modulation parameter $\lambda$ is inversely proportional to channel length:

while output resistance is calculated as:

Thus, open loop gain $g_m r_o \propto L$.

Gain and speed are a trade-off. By decreasing channel length, transition frequency is increased, and open loop gain is simultaneously decreased. Similarly, increasing channel length decreases transition frequency and increases open loop gain.

#### Gate Voltage

The next recommendation is for overdrive voltage $Vov=V_{gs}-Vth$ to be roughly 5% of $VDD$.

For high speed, $V_{ov}$ can be a larger value, such as 10% of $VDD$.

Note: While CMOS lacks in in-depth analysis showing why it is so, it can be shown that $g_m \approx W C_{ox}' v_{sat}$ still increases as a function of overdrive voltage.

Increasing $V_{ov}$ increases effective mobility and thus gain. At the same time, increasing $V_{ov}$ also increases $f_T$, as shown above. The result is a larger gain-transition frequency product, GFT.

### Gate Width

According to CMOS section 9.2.1,

The width of the MOSFET is selected to ensure the MOSFET has enough current drive for a particular load.

The tradeoff here is current drive (which impacts speed), and power.

As a first cut, let's select for a bias current of 10uA

$I_d$ versus $V_{DS}$, W/L=80/4

A W/L of 80/4 seems to do the trick. Due to the early effect, the bias current varies with $V_{DS}$. As in CMOS, we can simple say the drain current is 10 uA as an approximation. Channel length modulation parameter $\lambda$ can be estimated from the graph to be approximately 0.32 $V^{-1}$.

### Output Resistance

Output resistance is defined as:

We can see this analytically in the following plot, which is the reciprical of the derivative of the $I_D$ versus $V_{DS}$ plot above.

$r_o$ as a function of $V_{DS}$, W/L=80/4

$r_o$ varies from 400-450k$\Omega$ for $V_{DS}$ > 300mV. We can say it is 400k$\Omega$ as an approximation. The peak output resistance at $V_{DS}$ = 500mV can be exploited in the design of current mirrors.

To determine $V_{DS, sat}$, we look at when $r_o$ begins to increase, around $V_{DS}$ = 60 mV. Note this is different than the overdrive voltage of 90 mV, as saturation voltage and overdrive voltage differ in short channel processes.

### Forward Transconductance

Forward Transconductance is defined as:

$g_m$ as a function of $V_{GS}$, W/L=80/4

Looking at the graph, $g_m$=170 uA/V at $V_{GS}$=500mV.

Thus, open loop gain is:

### Transition Frequency

Finally, let's determine transition frequncy $f_T$ analytically.

Gain as a function of frequency, W/L=80/4

As we can see in the plot above, the gain becomes 0dB at 1.08 GHz frequency.

To determine the gain-frequency product GFT, we multiply open loop gain by transition frequency:

## Conclusion

Here is the table that summarizes the results. Analogous PMOS values will soon be generated.

W/L 80/4 in units of $\lambda$
$V_{DS, sat}$ 60mV
$V_{ov}$ 120mV
$V_{GS}$ 500mV
$V_{th}$ 380mV
$v_{sat}$ $1.12 \times 10^5$ m/s
$g_m$ 170 uA/V at $I_D$=10uA
$r_o$ 400k$\Omega$ approximate at $I_D$=10uA
$g_m r_o$ 68 V/V open circuit gain
$\lambda$ 0.32 V^-1 CLM parameter, at L=4
$f_T$ 1.08 GHz approximate at L=4